This invention relates generally to direct digital synthesis circuits and in particular to direct digital synthesis circuits which produce multiple output signals with selectable phase offset between the signals.
Direct digital synthesis (DDS) is a technique by which waveforms stored as digital waveform patterns in a waveform memory are reproduced as output signals using a digital to analog converter (DAC). A phase accumulator consisting of a digital register and adder contains a phase accumulator value which is incremented at a dock rate with a selectable phase increment, thereby determining the output frequency of the output signal. Phase accumulators can be constructed from inexpensive digital adders and latches to obtain a relatively large number of available bits to obtain precise control over the frequency of the output signal. The higher order bits (most significant bits) from the phase accumulator are provided as a series of addresses to the waveform memory which in turn provides digital waveform data to the DAC according to digital waveform patterns stored in the waveform memory. The DAC in turn produces the output signal from the digital waveform data.
It is often desirable to add additional output signals which are reproduced synchronously with the first output signal, with each additional output signal having a selectable phase offset from the first output signal. DDS technology has been adapted to provide multiple, synchronized waveforms with selectable phase offsets. FIG. 1A and 1B illustrate the relationship between two synchronous output signals with a selectable phase offset created by a two-channel DDS synthesizer circuit. FIG. 1A is a graph of waveform 10 which represents an output signal from channel 2 of a two-channel DDS synthesizer circuit. FIG. 1B is a graph of waveform 20 which represents an output signal from channel 1 of the two-channel DDS synthesizer. The waveforms 10 and 20 can be the same or different wave shapes based on the digital waveform patterns stored in the waveform memory but each waveform is related by having the same number of digital waveform values in its digital waveform pattern. The period for one cycle of the digital waveform pattern is the time difference t3 -t1 for waveform 10 which equals the period for one cycle of the waveform 20 which is t2-t0. The phase offset may be measured as a time difference, in this case as the time t1-t0, or as a fraction of the period, measured in degrees.
Two-channel DDS synthesizers that are capable of generating waveforms with selectable phase offset are known in the art. The second channel is typically obtained by adding a second parallel DDS synthesizer alongside the first DDS synthesizer and coupling a common clock signal to each synthesizer and then entering a predetermined phase offset value into one of the phase accumulators. Because the phase accumulator values are continually incremented by the same phase increment value according to the same clock signal, the desired phase offset between the two output signals from the first and second channels is maintained.
FIG. 2 is a simplified block diagram of a two-channel DDS synthesizer circuit according to the prior art. ADDS synthesizer 100 produces an output signal which may take the form of waveform 20 (shown in FIG. 1). A phase accumulator 110 is constructed from a phase adder 120 which has an output A+B coupled to a latch 130 via a parallel data path. The latch 130 has an output D coupled to an input A of the accumulator 110 via a second parallel data path. In the preferred embodiment, each of the parallel data paths in the phase accumulator is 28 bits wide. Wider data paths may be readily employed where a greater amount of frequency precision in the output signal is required. A phase increment value 140 is obtained from a microcontroller (not shown) and is coupled to an input B of the phase accumulator 120 to control the output frequency of the output signal 20.
A clock signal 125 is coupled to a clock input CLK on the latch 130 to determine the rate at which the phase increment value 140 is added to the present contents of the phase accumulator, represented by a phase accumulator value. The rate of the clock signal 125 and the value of the phase increment value 140 determine the rate at which the values in the phase accumulator value is incremented. One cycle of the output waveform 20 is complete when the phase accumulator value stored in the phase accumulator 110 reaches its maximum value. As the phase accumulator value exceeds the maximum capacity of the phase accumulator 110, the phase accumulator 110 "wraps around" back through its zero value to continue into a new cycle of the output waveform 20. In this way, the waveforms 10 and 20 may be reproduced as continuous waveforms and with the desired phase offset between the waveforms 10 and 20 continuously maintained.
The most significant bits from the phase accumulator 110 are coupled to an address input of a waveform random access memory (RAM) 150. In this way, the memory locations of the waveform RAM 150 are sequentially accessed at a sample rate which is determined by the rate of the clock signal 125, phase increment value 140, and the number of bits of the phase accumulator 110. A data output from the waveform RAM 150 is coupled to a DAC 160 which converts the digital waveform data to analog voltage values at the sample rate to produce the output signal.
A second DDS synthesizer channel is implemented using a second, parallel DDS synthesizer 200 which functions in a manner substantially similar to that of the DDS synthesizer 100. DDS synthesizers 100 and 200 share the clock signal 125. A phase offset value 210 is coupled to a preset input of the latch 130 which is added to the phase accumulator value stored in the phase accumulator 130 to obtain an address value for the waveform RAM which contains the desired phase offset from the phase accumulator value stored in the phase accumulator 230. Alternatively, the phase offset 210 could be coupled to a preset input of the latch 250 instead of the latch 130 to obtained the desired phase offset. The phase offset value 210 is obtained from a microcontroller (not shown) but is generally controllable to obtain a desired phase offset. The phase increment value 140 is coupled to both adders 120 and 260. The waveform data from the waveform RAM 240 are coupled to a DAC 270 to produce the waveform 10 with the phase offset as shown in FIG. 1A.
The phase accumulators 110 and 230 and waveform RAM 150 and 240 are substantially identical and perform the same function for each channel between the two DDS synthesizers 100 and 200. Care must be taken to synchronize the two phase accumulators to the desired starting points to obtain the desired phase offset. If a new phase offset is desired, it is necessary to first synchronize the two phase accumulators by entering a zero reset value in of the latches 130 and 250, and then entering a new phase offset value at the preset input of the latch 130, thus interrupting the output signals during the change. Therefore, it would be desirable to provide a two-channel DDS synthesizer employing a waveform interleaving circuit which requires a single phase accumulator and a single waveform RAM. It would be further desirable to have at least two waveform patterns contained in the waveform RAM which may be selected for either channel and to have the capability of adjusting the phase offset with no interruption of the output signal.